Formal Methods in Systems Engineering   

Technische Universität Darmstadt

 

X Photograph of Helmut Veith **** NEWS: Starting December 1, I am affiliated with Vienna University of Technology. ****

 
Prof. Dr. Helmut Veith

Formal Methods in Systems Engineering
TU Darmstadt
Hochschulstr. 10
D-64289 Darmstadt

veith (at) cs.tu-darmstadt.de

+49-6151-16-7351
+49-6151-16-7372  (sec)
+49-6151-16-7374  (fax)

 


Papers at scholar.google
Papers at DBLP

FORSYTE Papers

Selected Events

CSL 2010 (PC co-chair)
Decision Procedures in
SW, HW, Bioware 2010

FMCAD 2009
ICTAC 2009
CAV 2009
CSR 2009
EC2 2009
WING 2009
CSL 2009
LPAR 2008 (PC co-chair)
CSR 2008
Alpine Verification 2008
CSL 2007
LPAR 2007
25 Years of Model Checking
CSR 2007
Alpine Verification 2006
FSTTCS 2006
EAAI 2006
Alpine Verification 2005
CAV 2005
VISSAS 2005
LICS 2004
SYNASC 2004
SYNASC 2005
SYNASC 2006
SYNASC 2007
CAV 2003
CSL 2003 / KGS 2003


 

 

 

 

25 Years of Model Checking
LNCS vol. 5000, Springer


PhD Students

Andreas Holzer
Visar Januzaj
Alexander Karbyshev
Johannes Kinder
Mohammad Khaleghi
Stefan Kugele
Boris Langer
Michael Tautschnig
Florian Zuleger

Graduated

Stefan Katzenbeisser
Marko Samer
Christian Schallhart

Helmut Veith is a professor at  the Computer Science department of TU Darmstadt, and an
adjunct professor at Carnegie Mellon University. He holds a diploma in Computational Logic and
a PhD sub auspiciis praesidentis in Computer Science, both from Vienna University of Technology.
Prior to his appointment to Darmstadt, he was a professor at TU Munich and an associate professor
at TU Vienna.

In his research, Helmut Veith applies formal and logical methods to problems in technical
computer science and software technology. His current work is focussing on model checking,
software verification and testing, embedded software and computer security.

Helmut Veith is an executive board member of the Kurt Goedel Society and the European
Association on Computer Science Logic
.


Current Research Topics
Software Verification
Model Checking
Program Testing
Parameterized Verification
Embedded Systems Engineering
Counterexample-Guided Abstraction Refinement
Vacuity Detection
Analysis of Executables
Malware Detection
Intellectual Property Protection
Security for Virtual Worlds
Temporal Logic Query Solving
Shape Analysis
Performance Analysis

Recent Talks

Ptolemaic Abstraction
EPFL Lausanne, February 2009

Danger Inside: Computer Errors in the Infrastructure
Invited Speaker at Europaeisches Forum Alpbach, August 08
[ Streaming Video] (go for Informations- und Kommunikationsinfrastrukturen)

Lust auf Informatik
TU Darmstadt, October 08

Dagstuhl Workhshop on VLSI and Distributed Algorithms, September 08
Model Checking: From Proofs to Automation

Keynote Talk at FIT-IT Embedded Systems, Vienna, May 08
Embedding Formal Methods into Systems Engineering

Invited Speaker at LPAR 07, October 07
On the Notion of Vacuous Truth


Media Appearences

Radio Interview, OE1, August 08
Computer Errors in the Infrastructure [MP3]


TV interview, Austrian Television (Zeit im Bild), April 08
Model Checking [MP4]

 


Selected Projects

Model Checking and Testing
PUMA Graduiertenkolleg (DFG)
Determination of Loop Bounds (Microsoft Research)
FORTAS (DFG), jointly with Real Time Group at TU Vienna (FWF)
GAMES Network (EU)

Embedded Software
baseXT (BMW)
TAMORR, AIDA (EADS)
Inteco (Diehl Aerospace)

Computer Security
CASED Center at TU Darmstadt
Bayerische Elitefoerderung
ECRYPT Network (EU)

Computational Science
with Chemistry Applications (EU TEMPUS), with Vienna and Uzbekistan

 

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